ER Engineering Highlights Advanced Packaging Technologies
ER Engineering Corp. is set to present its latest innovations in laser and plasma technology during SEMICON Taiwan 2025, scheduled for September 10-12 at the Taipei Nangang Exhibition Center. As the semiconductor industry evolves with significant advancements in AI, high-performance computing (HPC), and 5G technologies, advanced packaging has emerged as an essential strategic area. According to projections by Yole Group, the market for advanced packaging is expected to exceed $50 billion by 2025, showing an impressive annual growth rate of over 15%, particularly for fan-out panel-level packaging (FOPLP).
Innovative Solutions on Display
ER Engineering will showcase a comprehensive range of solutions including FOPLP technologies, Through-Silicon Via (TSV), Through-Glass Via (TGV), and plasma dicing. These fully integrated processing technologies aim to assist customers in managing high-density I/O requirements, controlling warpage, and achieving ultra-thin features.
FOPLP Technology
The FOPLP solutions by ER include an array of equipment such as laser marking, plasma dicing, and laser debonding. Designed for substrate sizes up to 700×700 mm, these machines combine precision control with stable processing capabilities, even accommodating substrate warpage up to 16 mm. This level of functionality caters to the increasing demand for efficient manufacturing processes in the advanced packaging sector.
TSV Innovations
With the rise of 3D packaging and advanced memory technologies, TSV has become a vital component for high-density integration. ER’s offerings for TSV applications include advanced drilling, cleaning, and via debonding solutions that leverage both laser and plasma technologies. This approach ensures precision via profiles, minimal defect rates, and reliable interconnections across all wafer sizes and materials.
Glass Substrate Solutions
In the emerging sector of glass core substrates, ER's laser modification technology has achieved extraordinary results, such as via circularity greater than 0.9, aspect ratios of 101, and the capability to drill up to 1,500 vias per second. This technological advancement supports the manufacturing of CoPoS and ABF substrates, promoting high-yield and high-performance outcomes. Together with partners like E-core, ER will introduce a comprehensive process for glass substrates at the event, facilitated by complete metallization capabilities.
Comprehensive Support for Package Technologies
All of ER's equipment is designed, manufactured, and qualified in Taiwan, utilizing components sourced from leading US and European suppliers. Over 500 systems have already been shipped worldwide, with ER's solutions being widely deployed in FCBGA, FCCSP, fan-out and wafer-level packaging by prominent OSATs and IDMs. Furthermore, the company has expanded its BGA Flip Chip offerings, providing plasma cleaning for chip adherence pre-flipping, in-mold and underfill cleaning, and laser marking for traceability. In addition, 2025 sees the launch of a fully automated high-power burn-in solution, capable of supporting testing environments up to 3,000W.
ER Engineering warmly invites industry partners to visit its booth and explore next-generation encapsulation and dicing technologies alongside its technical team at SEMICON Taiwan 2025.
Event Details:
Location: Taipei Nangang Exhibition Center, Hall 1
Booth: 4F, #N0968
Dates: September 10-12, 2025
Website: ER Engineering