Achronix Unveils Cutting-Edge JESD204C IP Core for Speedster7t FPGAs Targeting Advanced Data Conversion

Achronix Introduces the JESD204C IP Core for Speedster7t FPGAs

Achronix Semiconductor has made waves in the semiconductor industry by announcing the availability of its JESD204C IP core designed for the Speedster®7t FPGA family. This innovative IP core is expected to significantly enhance the performance and efficiency of next-generation wideband converter systems. With the ability to handle data rates up to 32 Gbps per lane and support for multiple lanes, the JESD204C core enables an impressive aggregate serial line rate of up to 256 Gbps. When combined, four cores can achieve an astounding performance of up to 1 Tbps.

As businesses and industries transition to advanced technologies like artificial intelligence (AI), the demand for higher sample rates and resolution in data conversion is surging. The JESD204C IP core not only meets these demands but also ensures a smooth integration with existing systems based on JESD204B standards, allowing for easy migration while minimizing developmental risks. This compatibility is crucial for manufacturers looking to upgrade their legacy systems without incurring prohibitive costs or time.

Jay Aggarwal, Senior Director of Product Marketing at Achronix, emphasized the importance of this new core, stating that, “AI is creating new performance requirements in markets that have always depended on fast, precise data conversion.” He explained that the JESD204C IP core combines advanced interface features with the proprietary architecture of Speedster7t, which includes 112 Gbps SerDes, a 2D network-on-chip design, and high-bandwidth memory interfaces, all tailored for real-time data processing.

Key Features of the JESD204C IP Core

1. Scalable Throughput: This core supports throughput of up to 32 Gbps per lane, allowing for seamless connectivity with high-speed analog-to-digital (ADC) and digital-to-analog converters (DAC).
2. Encoding & Error Correction: Robust encoding options include 64b/66b and 8b/10b modes, along with features such as Forward Error Correction (FEC) and cyclic redundancy checks (CRC-12, CRC-3).
3. Phase-Coherent Synchronization: It supports deterministic latency, making it ideal for both single-channel and multi-channel applications.
4. Robust Integration: The design includes flexible framing and integrated features for alignment and recovery, along with an AXI-Lite interface to simplify control.

Speedster7t Architecture Capabilities

Designed for high-performance applications, Speedster7t FPGAs are powered by 112 Gbps SerDes technology that guarantees great signal integrity necessary for maintaining high-speed connectivity of the JESD204C core. The architecture is equipped with a 2D NoC that enhances bandwidth transport across the device, significantly reducing concerns around power consumption and programmable routing congestion.

Additionally, this FPGA family is unique in its support for embedded GDDR6 memory controllers, which allow for an aggregate bandwidth of up to 4 Tbps. This capability proves invaluable for applications that require rapid processing of extensive datasets, such as AI inference and signal processing.

Target Industries

The introduction of the JESD204C IP core is poised to impact various sectors, including:

- Wireless Infrastructure: As the world moves closer to 5G/6G connectivity, direct-RF transceivers and AI-assisted spectrum optimization are becoming imperative.
- Aerospace & Defense: Applications include radar systems, electronic warfare, and synchronized multi-channel AI-assisted detection capabilities.
- Test & Measurement: The need for high-bandwidth oscilloscopes and automated testing equipment drives the demand for advanced data conversion technologies.
- Edge Processing: Applications in medical imaging and scientific instrumentation will benefit from the higher data capture rates enabled by this technology.

Availability and Evaluation

The JESD204C IP core is currently available for implementation in Speedster7t FPGAs. To facilitate quick evaluations, Achronix provides a time-limited evaluation version of the core. Interested customers can access product documentation or request an evaluation version through their website.

In summary, as the demand for rapid data processing and analysis continues to grow, Achronix’s JESD204C IP core is set to deliver robust, high-performance solutions tailored for modern technological challenges, reinforcing the company’s position at the forefront of the semiconductor industry. For further details, you can visit www.achronix.com.