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HUAWEI's Revolutionary Tau Scaling Law

In an exciting development for the semiconductor industry, HUAWEI recently introduced the Tau (τ) Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems, held in Shanghai. This landmark announcement by He Tingbo, President of HUAWEI's Semiconductor Business Department, presents a novel approach to semiconductor evolution, positioning itself as a successor to the aging Moore's Law.

A Shift in Focus: Time Scaling rather than Geometric Scaling

Traditionally, the semiconductor industry achieved performance improvements by shrinking transistor sizes—following Moore's Law, which stated that the number of transistors on a microchip doubles approximately every two years, leading to increased performance and reduced costs. However, this method is becoming increasingly complex and less cost-effective due to physical limitations. The Tau Scaling Law proposes a significant shift from this geometric scaling model to a time-based scaling approach. By focusing on reducing signal propagation delays and overall system execution time, HUAWEI aims to enhance performance and energy efficiency while maximizing transistor density.

Innovative Technologies Driving the Change

HUAWEI's new framework is underpinned by groundbreaking technologies such as LogicFolding and a multi-level optimization framework that spans devices, circuits, chips, and systems. The underlying goal of these innovations is to address the challenges faced due to resistance and capacitance at the physical layer. He Tingbo emphasized the need for a parameter that strikes a balance between improved performance and energy savings—an initiative that the Tau Scaling Law strongly supports.

• - Reducing Layer Delays: The Tau Scaling Law operates on the principle of reducing both transistor and interconnect resistance as well as parasitic capacitance. This minimizes delays on the physical layer, ensuring that signals travel faster.

• - LogicFolding Architecture: This advanced architecture restructures circuit layouts strategically, effectively shortening critical signal paths. As a result, there is a reduction of resistive and capacitive loads, which in turn elevates performance and transistor density.

• - Optimized Chip-Level Design: At the chip level, HUAWEI employs coordinated software architecture alongside silicon design to optimize both instruction and data flow, which significantly boosts parallel processing capabilities while concurrently reducing end-to-end execution time.

• - UnifiedBus Protocol: HUAWEI’s UnifiedBus interconnect protocol enhances memory addressing and native semantics for its large-scale computing systems, reducing latency and improving communication across numerous nodes.

Practical Applications of Tau Scaling

He revealed that HUAWEI has already begun implementing the Tau Scaling Law in a variety of products, particularly in smartphones and AI computing systems. Over the past six years, the company has designed and mass-produced an impressive total of 381 chips that leverage this innovative framework across various industries—significantly affecting its market reach.

Additionally, HUAWEI announced that its upcoming Kirin processors, set for release in the fall of 2026, will be the first to utilize the LogicFolding architecture, indicating a substantial leap in chip performance and efficiency.

Long-term Vision and Collaboration

The vision for the future is ambitious. HUAWEI projects that, by 2031, its advanced chips developed under the Tau Scaling framework could achieve remarkable transistor densities on par with 14-angstrom (1.4 nm) process technologies. However, He Tingbo stressed that the evolution of semiconductors is a collective challenge and will require collaboration among companies. No single entity can navigate the complexities of this industry alone, highlighting the importance of partnerships moving forward.

Conclusion

With the Tau Scaling Law, HUAWEI is setting a new path for semiconductor technologies, moving away from traditional constraints and towards a future where efficiency, performance, and collaboration are paramount. This bold initiative could potentially reshape the landscape of the semiconductor industry, making way for faster, smaller, and more energy-efficient chips.