#United States #San Jose #S2C #RISC-V #Andes Technology

Accelerating Chip Development with RISC-V Co-Emulation

In a significant advancement for the chip design industry, S2C, MachineWare, and Andes Technology have collaborated to unveil a cutting-edge co-emulation solution aimed at simplifying the increasingly complex landscape of RISC-V-based chip design. This innovative approach blends the strengths of their respective technologies to create a cohesive environment for hardware and software verification, thus streamlining the entire development process.

Addressing Complexity in RISC-V Design

As the demand for high-performance, customized architectures in RISC-V designs surges, so too do the challenges associated with pre-silicon software development and system validation. The newly introduced solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, along with Andes’ high-performance AX46MPV RISC-V CPU core. This integration aims to support a collaborative verification approach, allowing hardware and software teams to work in parallel, reducing overall development time and project risks significantly.

MachineWare's SIM-V Virtual Platform

Central to this co-emulation solution is MachineWare's SIM-V, a high-speed full-system virtual platform built on the SystemC TLM-2.0 framework. SIM-V not only promises exceptional simulation speed but also offers extensive compatibility with an array of third-party tools for debugging, testing, and coverage analysis. The platform is designed to provide precise instruction-accurate reference models that fully encompass the AndeStar V5 Instruction Set Architecture, along with the RISC-V Vector extension. This enables designers using the SIM-V Extension API to model, validate, and debug bespoke processor enhancements within a comprehensive system simulation featuring detailed visibility.

Lukas Jünger, CEO of MachineWare, emphasized the importance of this tool for customers, stating, "Our customers need tools that accelerate development without compromising accuracy. This co-emulation solution allows them to validate hardware and software concurrently, mitigates integration risks, and accelerates their time to market."

Andes Technology's High-Performance RISC-V Cores

Andes Technology adds to this collaboration with its advanced CPU intellectual property, including the high-performance AX46MPV multicore processor. This 64-bit RISC-V CPU can support up to 16 cores, features a sophisticated multi-level cache structure, and is equipped with a powerful Vector Processing Unit (VPU) boasting up to a 1024-bit Vector Length (VLEN) with High-Bandwidth Vector Memory (HVM). The AX46MPV is perfectly suited for applications requiring heavy computation, such as data-center AI workloads and high-performance modules in networking and storage domains.

Dr. Charlie Su, President and CTO of Andes Technology, highlighted the unique benefits these RISC-V cores provide, noting that customers appreciate the performance, robustness, and the opportunity to add custom extensions to enhance their applications. He stated, "By collaborating on this co-emulation method with MachineWare and S2C, our clients can assess their software stack's performance and design optimally before investing in costly silicon tapeouts."

S2C: Bridging Virtual and Physical Worlds

S2C's role in this collaboration is crucial, as it connects MachineWare's SIM-V platform to real hardware through its Genesis Architect and Prodigy FPGA prototyping systems. This innovative hybrid arrangement allows CPU models to run on the SIM-V platform while peripheral subsystems operate at speed on FPGA devices, interlinked by a high-speed transactional bridge. Such a setup permits realistic system implementations capable of executing complete software stacks, offering unparalleled debug visibility throughout the development cycle.

Key Benefits and Future Perspective

The integration of these three entities significantly supports various critical development stages, including:

• - Pre-silicon software development
• - Hardware/software co-verification
• - System performance analysis and tuning
• - Custom ISA extension debugging

Ying, VP of S2C, explained, "With co-emulation, our customers can reduce costs, hasten time-to-market, and ensure software quality while benefiting from both cycle-accurate debugging and swift execution. This collaborative effort allows us to build on the high-performance advantages of hardware-assisted verification to deliver comprehensive shift-left solutions across the industry."

As S2C, MachineWare, and Andes move forward, their commitment to enhancing verification methodologies and developing robust, scalable tools for the RISC-V community remains steadfast. Their collaborative endeavor aims not only to improve individual product offerings but also to strengthen the overall ecosystem for next-generation RISC-V chip designs, promising exciting advancements in technology and innovation for the future.