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Synopsys and TSMC Unveil Angstrom-Scale Innovations in EDA

In a groundbreaking collaboration, Synopsys, Inc. has partnered with Taiwan Semiconductor Manufacturing Company (TSMC) to develop certified Electronic Design Automation (EDA) flows tailored for TSMC's latest advanced processes, namely A16™ and N2P. This collaboration aims to deliver optimized performance in semiconductor design, particularly in the realm of artificial intelligence (AI) chips and multi-die innovations.

A Leap Forward in Chip Design

The announcement emphasizes the introduction of certified digital and analog design flows, facilitated by Synopsys.ai™, which enhance design productivity while simplifying the transition for analog designs. Current developments are also underway for EDA flows on TSMC's A14 process, further solidifying Synopsys' commitment to supporting cutting-edge semiconductor designs. This collaboration reflects a strategic move to bolster design quality and accelerate time-to-market for next-generation System on Chip (SoC) technologies.

Collaborative Efforts in 3D Stacking Technologies

One of the significant features of this partnership is the advancement in 3D integration capabilities. Synopsys has collaborated with TSMC to certify the Synopsys 3DIC Compiler, which supports TSMC's CoWoS® technology, allowing for larger reticle sizes that facilitate the integration of 3D stacked dies—critical for enhancing performance in AI chips. By leveraging both 3D stacking and the 3Dblox standard, designers can now explore design potentials, validate prototypes, and efficiently manage floorplanning, leading to productive multi-die designs.

As highlighted by Synopsys Senior Vice President Sanjay Bali, “The collaboration between Synopsys and TSMC is transforming the semiconductor landscape, enabling engineers to push the frontier of technology further.”

Delivering High-Performance Outcomes

The latest improvements fostered by this partnership include enhanced backside routing capabilities, which optimize power distribution and overall design performance on TSMC A16™ chips. The Fusion Compiler has also seen enhancements to its frequency optimization engine, which is designed to significantly boost design efficiency. Moreover, Synopsys IC Validator™ has been certified for both A16 and N2P processes to ensure compliance with critical design rule checks.

This concerted effort illustrates the ongoing commitment of Synopsys and TSMC to drive industry-leading results while reducing risks associated with design integration. The expanded foundation and interface portfolio offered by Synopsys supports the lowest power consumption across high-performance compute, edge, and automotive designs.

Next-Generation Interface and Foundation IP Solutions

The portfolio includes silicon-proven IP solutions for key standards such as HBM4, 1.6T Ethernet, PCIe 7.0, and more, ensuring that designers benefit from verified components that meet rigorous performance, power, and area specifications. The successful implementation of Synopsys IP in thousands of previous designs reflects the reliability and robustness of these solutions, enabling a seamless pathway to first-pass silicon success.

As the semiconductor industry looks towards the future, Synopsys and TSMC's partnership marks a significant leap forward. With ongoing developments and continuous integration of advanced technologies, both companies are well-positioned to redefine the boundaries of semiconductor design, ultimately accelerating the arrival of innovative solutions in the market.

Conclusion

Synopsys is set to showcase its advancements at the TSMC Tech Symposium Forum in Santa Clara, demonstrating the profound impact of its collaboration with TSMC. As they navigate the complexities of Angstrom-scale design processes, Synopsys continues to enhance its offerings, catalyzing the era of pervasive intelligence in the semiconductor industry.

For more information on Synopsys and TSMC's latest EDA solutions, please visit Synopsys' official website.