Marvell Unveils Pioneering 2nm Silicon for Next-Gen Infrastructure
On March 3, 2025, Marvell Technology, Inc., listed on NASDAQ under the symbol MRVL, revealed its first 2nm silicon integrated circuit, a significant milestone in the data infrastructure semiconductor sector. This advanced technology is not only set to elevate infrastructure performance but also promises enhanced efficiency, particularly in line with the burgeoning demands of artificial intelligence (AI) and cloud networking.
The Core of the 2nm Platform
Developed utilizing TSMC's cutting-edge 2nm process technology, Marvell’s new silicon is a pivotal part of its comprehensive platform designed to cater to custom AI accelerators, CPUs, and networking solutions. The innovative silicon integrates high-speed 3D input/output (I/O) capabilities that allow for vertically stacked chiplet die, bringing unprecedented performance improvements to industry standards.
Projected to experience an annual growth of 45% in total addressable market (TAM), custom silicon is anticipated to represent roughly 25% of the accelerated computing market by 2028. This growth signals a shift towards more tailored silicon solutions in a rapidly evolving tech landscape.
Building Block Strategy
Marvell is adopting a strategic 'building block' approach in its platform development. This involves creating a diverse portfolio of semiconductor intellectual property (IP) that includes electrical and optical serializer/deserializer (SerDes) technologies, die-to-die interconnects for both 2D and 3D devices, and advanced packaging techniques. Such innovations will pave the way for the development of cutting-edge technologies like custom high-bandwidth memory (HBM), optical digital signal processors (DSPs), and high-performance switches.
Sandeep Bharathi, chief development officer at Marvell, emphasizes the importance of these advancements: “Our platform approach enables us to accelerate the development of market-leading high-speed SerDes and other critical technologies on the latest processing nodes.” This leap is significant, allowing both Marvell and its clientele to enhance expedited infrastructure technologies.
Advancing Performance with 3D I/O
A standout feature of Marvell's 2nm platform is the introduction of 3D simultaneous bi-directional I/O. This new I/O technology operates at an impressive speed of up to 6.4 Gbits/second, enabling connectivity between vertically stacked chiplet die. In contrast to traditional unidirectional I/O, this bi-directional approach doubles the bandwidth potential while halving the necessary connections.
The benefits of this technology extend to chip designers as well. As contemporary microchips often exceed the dimensions of a reticle—the projection mask used in photolithography—implementing multiple chiplets within a single package is now a strategic necessity. With 3D simultaneous bi-directional I/O, designers can create taller stacks accommodating more dies and thereby achieving capabilities surpassing that of traditional monolithic systems.
Collaborative Innovations
Marvell's collaboration with TSMC has been instrumental in the evolution of its 2nm platform. Dr. Kevin Zhang, TSMC's senior vice president, acknowledged the significance of this partnership, stating, “We look forward to our enduring collaboration with Marvell, harnessing TSMC's advanced silicon technology and packaging solutions to further the development of accelerated infrastructure.”
Conclusion
As technological demands continue shifting towards AI and cloud computing, Marvell's latest 2nm silicon marks a revolutionary step in the semiconductor field. By laying the groundwork for innovative AI infrastructures and ensuring superior performance and efficiency, Marvell positions itself at the forefront of semiconductor technology revolution. This technological leap not only signifies progress for Marvell but also holds transformative potential for the global landscape of data infrastructure in the AI era.
For more details on Marvell's initiatives, visit
Marvell's official website.